The present invention relates to integrated circuit generation, and more specifically, to variable accuracy incremental timing analysis.
The generation of an integrated circuit (i.e., chip) involves a number of phases including the high-level logic design, logic synthesis, physical synthesis, routing, and manufacturing phases. Each of the phases can include multiple processes that can be performed iteratively. An electronic design automation (EDA) tool can be used to perform many of the processes such as processes that are part of the logic synthesis and physical synthesis phases. The logic design can provide a register transfer level (RTL) description. The physical synthesis phase includes identifying and placing components, such as gate logic, to implement the logic design. A netlist can be produced to indicate the interconnections among components. In the routing phase, the placement of wires that connect gates and other components in the netlist is defined, and in the manufacturing phase, the finalized design is provided for physical implementation of the chip. In addition to functional requirements, an integrated circuit must typically also meet timing and power constraints. To ensure that timing requirements are met, timing analysis can be performed at different phases and iteratively.